In a class of integrated circuits referred to here as general purpose microcontrollers, a single microcontroller integrated circuit design is generally to be used by many different customers in many different applications. Due to the different customers and applications, it is often the case that the same microcontroller integrated circuit design is to be usable with many different types and/or sizes of memory devices. Such general purpose microcontrollers therefore may include configurable on-chip memory controllers. By appropriate configuring of an on-chip memory controller, the memory controller can be made to interface to a selected one of many different memory types, memory sizes, and memory bus configurations.
FIG. 1 (Prior Art) is a diagram of a part of one conventional microcontroller integrated circuit design. Microcontroller 1 involves a processor 2, a local bus 3, two memory controllers 4 and 5, as well as other circuits not illustrated. Processor 2 can access external memory devices 6 and 7 across a first data bus 8. Processor 2 can also access external memory devices 9 and 10 across a second data bus 11. Because the data buses 8 and 11 are separate, and because two memory controllers 4 and 5 are coupled to the buses as illustrated, memory controller 4 can perform an access across data bus 8 at the same time that memory controller 5 can perform an access across data bus 11. Memory controllers 4 and 5 may, for example, be of identical construction and may have identical capabilities. Such memory controllers are often configurable by the processor so that the microcontroller integrated circuit can use data buses of a selected one of several different widths to interface to external memory devices. Depending on the width of a data bus coupled to various terminals associated with memory controller 4, memory controller 4 can provide a data bus interface of, for example, sixteen bits, twenty-four bits, or thirty-two bits. In this example illustrated in FIG. 1, however, all memory devices on a particular data bus are of the same sixteen bit data width.
FIG. 2 (Prior Art) is a diagram of another conventional design. In this case, a microcontroller 12 can, in a given external bus operation, access either memory device 13 or memory device 14. Memory device 13 stores data words of a relatively narrow width (for example, each memory location is sixteen bits as illustrated), whereas memory device 14 stores data words of a relatively wide width (for example, each memory location is thirty-two bits as illustrated). If memory device 13 is being accessed, then only sets 15 and 16 of data conductors and sets 17 and 18 of data terminals are employed to communicate 16-bit words of data between microcontroller 12 and memory device 13. Sets 19 and 20 of data conductors and sets 21 and 22 of data terminals are not needed or used for such accesses. If, however, wide memory device 14 is being accessed, then all sets 15, 16, 19 and 20 of data conductors are used and all sets 17, 18, 21 and 22 of data terminals are employed to communicate 32-bit words of data between microcontroller 12 and memory device 14. How many of the data conductors and data terminals are used depends on the memory location that processor 23 is attempting to access. If the memory location is in memory device 13, then fewer than all of the data bus conductors and data terminals are employed as appropriate, whereas if the memory location is in memory device 14, then all of the data bus conductors and data terminals are employed. An alternative and/or improved microcontroller, memory controller and memory architecture is desired.